1. Field of the Invention
The present invention relates generally to integrated circuits and their fabrication processes. More specifically, the present invention relates to an integrated circuit fabrication process for making multi-threshold-voltage,"Vt," integrated circuits and the devices fabricated with the process.
2. Description of Related Art
A common integrated circuit transistor device is the Metal Oxide Semiconductor Field Effect Transistor, or "MOSFET." A typical MOSFET structure includes a pair of source/drain regions implanted into a surface of a silicon substrate, a gate oxide thin film formed on the substrate between the source/drain regions, and a gate electrode structure formed on the surface of the gate oxide. The region of the substrate itself between the source/drain regions is known as the channel region. The length of the channel region, "Lc," is the distance between the source/drain regions. Typically, the channel length is less than the gate length, "Lg," measured in the same dimension.
The threshold voltage, Vt, for a MOSFET device is defined as the applied gate-to-source voltage, "Vgs," below which the MOSFET device drain-to-source current, "Ids," becomes effectively zero (although a drain-to-source leakage current may still be present, it is considered negligible). The threshold voltage, Vt, is a function of a number of parameters, including gate material, gate insulation material and thickness, channel doping levels, impurity levels, source-to-substrate voltage, and the like as would be known to a person skilled in the art.
A prior art process is shown in FIGS. 1a-1f. FIG. 1a depicts a silicon substrate material 10 that has a first conductivity type (e.g., for NMOS, having boron or BF.sub.2 impurities; for PMOS having arsenic or phosphorous impurities, at a first concentration level). A threshold adjust implant, represented by arrows 12, forms a substrate surface layer 10a having a higher, second concentration of first conductivity type impurities. Typically, the impurity doping is at an injection energy of about 5-to-15 KeV at a concentration of about 8.times.10.sup.12 ions/cm.sup.2. As shown in FIG. 1b, a gate oxide 14 is grown on the substrate surface region 10a. Next, as illustrated by FIG. 1c, a gate electrode 16 structure, comprising a pillar of polysilicon is deposited on the gate oxide 14 and etched. Thereafter, as shown in FIG. 1d, lightly-doped source/drain ("LDD") regions 18 are implanted with second conductivity type impurities, represented by arrows 19, at self-aligning positions with respect to the gate electrode 16 structure. For an exemplary NMOS device, arsenic ions are typically implanted at a concentration range of about 1.times.10.sup.14 to 1.times.10.sup.15 ions/cm.sup.2 at about 5 KeV. Looking to FIG. 1e, sidewall spacers 20, serving as insulating films, are formed by deposition and etching to each side of the gate electrode 16 pillar. Finally, as depicted in FIG. 1f, higher-doped source/drain regions 22 are implanted, represented by arrows 23, self-aligning to the spacers 20 between the LDD regions 18 and the Vt adjust implant surface layer 10a. For the exemplary NMOS device, arsenic ions are implanted at a concentration of about 2.times.10.sup.15 ions/cm.sup.2 at about 5-to-10 KeV injection energy.
There is considerable technology developed for the manipulation of threshold voltage, Vt, referred to in the art as "Vt adjusts." See e.g.: A Novel Source-to-Drain Nonuniformly Doped Channel MOSFET for High Current Drivability and Threshold Voltage Controllability, Okamura et al., IDEM 90, pp. 391-394; or, U.S. Pat. No. 5,466,957, Yuki et al.; or, assignee's own U.S. patent application Ser. No. 08/949,959, Milec-Strakalj & Yeap, for A MOS Device with Self-Compensating Vt-Implants, and assignee's own U.S. patent application Ser. No. 08/914,986, Krivokapic, for a Self-Aligned Channel Transistor and Method for Making Same.
In certain types of integrated circuit devices, for example microprocessors having a cache memory, there is a need for transistors performing both high speed logic and low power consumption which is generally measured by the OFF-state leakage current (a function of gate length). The same transistor can not achieve both; a shorter gate length will inherently have a higher leakage current. One solution has been the use of semiconductor device structures having two different Vt adjust implants. This is a relatively costly process. As shown in FIGS. 2a-2c, it requires multiple Vt adjust implant steps to form devices with different Vt characteristics.
Another solution is the use of the use of two different gate oxide thicknesses. See e.g., A 0.18 um CMOS Logic Technology with Dual Gate Oxide and Low-k Interconnect for High-Performance and Low-Power Applications, Diaz et al., VLSI Technology Symposium 1999 report, proposing the support of 1.5-to-2 volt core logic as well as 3.3 volt periphery circuitry (input/output). As shown in FIGS. 3a-3c, it requires multiple etch steps. This is a relatively complex and more costly process.
Another solution is provided in accordance with the present invention.